A flash memory cell using a method in which a trench that is self-aligned with a stacked film pattern formed in the memory cell is used in element isolation has advantages that allow the distance between adjacent memory cells to be minimized so that the memory cells can be more densely arranged.
Such a method is disclosed in Japanese Patent Application 11-26731 (JPA 11-26731) and is illustrated in FIG. 14. FIGS. 14(a)-(c) are cross sections of a conventional semiconductor device after various processing steps.
Referring now to FIG. 14(a), a stacked film of a tunnel oxide film 204, a first floating gate electrode 203, and a nitride film 205 is formed on a semiconductor substrate 201. A trench 211 is then formed in the semiconductor substrate 201 using the stacked film pattern as a mask.
Referring now to FIG. 14(b), a buried oxide film 233 is then buried in the trench. Then, the nitride film 205 is removed and a second floating gate electrode 213 made of polysilicon is formed.
Referring now to FIG. 14(c), a capacitor film 214 and a control gate electrode 215 is formed. Control gate electrode 215 is made of polysilicon.
However, the conventional manufacturing method of a flash memory of this type can have problems. First, the reliability of the tunnel oxide film can be low. Second, the process can become complicated when forming the floating gate electrodes in a two-layered structure in order to implement a high capacitance ratio.
Adverse effects may result from the above-mentioned problems as will now be explained.
First, when a shallow trench isolation (STI) is formed with a self-aligned technology with respect to the floating gate electrode 203 of the first layer, a distance between a substrate edge (a trench shoulder portion) of the STI and a floating gate of the first layer can be short. This can create current leakage in a shoulder portion (A illustrated in FIG. 14(c)) of trench 211 during the operation time. Thus, holding characteristics can be deteriorated resulting in a reduced reliability in the tunnel oxide film.
Second, a width of the floating gate electrode 203 of the first layer is equal to a channel width. Thus, a capacitance ratio cannot be increased unless a surface area of a floating gate electrode opposite to the control gate electrode 215 is increased by forming the floating gate electrode 213 of the second layer to a width longer than the width of the floating gate electrode 203 of the first layer. Doing so, may increase the area consumed by each memory cell.
In view of the above discussion, it would be desirable to provide a semiconductor device such as a flash memory and its manufacturing method that may have a single-layer floating gate electrode structure without an influence of an electric field concentration in a trench shoulder portion during operation.